The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 09, 2007
Filed:
Mar. 05, 2003
Lynne A. Okada, Sunnyvale, CA (US);
Fei Wang, San Jose, CA (US);
James Kai, Santa Clara, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A method for forming an inlaid interconnect structure for ICs. The method includes forming an etch stop layer, opening a portion of the etch stop layer on an IC die, forming a dielectric layer and cap layer over the etch stop layer, forming a photoresist pattern, and etching the cap and dielectric to form an opening that is then filled with a conductive material (e.g., metal). The method may further include forming a barrier layer within the opening of the etch stop layer. According to another aspect of the invention, a first and second etch stop layer are formed over the substrate and the second etch stop layer is patterned to define two regions, wherein a second region having the first and second etch stop layers experiences a faster etch rate than the first region. The dielectric layer and cap layers are then deposited over both regions and two via or trench openings are formed therethrough in the regions, respectively. The first and second etch stop layers protect the underlying substrate from experiencing punchthrough during the via or trench formation. The etch stop layers are then removed in the openings and a conductive material is formed therein.