The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7278205 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 09, 2007

Filed:

Aug. 07, 2003
Applicants:

Masashi Miyazaki, Nakamuroda Haruna-Machi, JP;

Mitsuhiro Takayama, Nakamuroda Haruna-Machi, JP;

Tatsuro Sawatari, Nakamuroda Haruna-Machi, JP;

Takatoshi Murota, Nakamuroda Haruna-Machi, JP;

Inventors:

Masashi Miyazaki, Nakamuroda Haruna-Machi, JP;

Mitsuhiro Takayama, Nakamuroda Haruna-Machi, JP;

Tatsuro Sawatari, Nakamuroda Haruna-Machi, JP;

Takatoshi Murota, Nakamuroda Haruna-Machi, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/36 (2006.01);
U.S. Cl.
CPC ...
Abstract

A multilayer printed wiring board (PWB) including via holes with satisfactory quality without defective shapes like swelling or recession on the end faces is provided. The multilayer PWB includes a build-up board of plural insulation layers as the main structure. In each of the insulation layers, via holes (columnar conductors) for electrically connecting between conductor circuits on the base layer or adjacent layers are formed. The via holes are formed by patterning metal foil with conductivity. The height 'H' of the via holes (dimension in the thickness direction of the via hole forming layer) depends on the thickness 'D' of the original metal foil only. Accordingly, the via holes can be formed without carrying out filling with conductive paste or electrolytic plating. Thus, multilayer PWB having via holes with satisfactory quality without defective shapes like swelling or recession on the end faces can be manufactured.


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Miyazaki, Masashi. (2007). Multilayer printed wiring board and production method therefor (U.S. Patent No. 7278205). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7278205

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