The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 02, 2007
Filed:
Oct. 23, 2006
Applicants:
Bartosz Banachowicz, Santa Clara, CA (US);
Andrew Wright, Fremont, CA (US);
Inventors:
Bartosz Banachowicz, Santa Clara, CA (US);
Andrew Wright, Fremont, CA (US);
Assignee:
NetLogic Microsystems, Inc., Mountain View, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 15/00 (2006.01);
U.S. Cl.
CPC ...
Abstract
A memory/logic cell layout structure includes a pair of memory/logic cells formed on a substrate. Each memory/logic cell () can include a pair of memory areas to store data (----), and a logic portion (--) that receives the data stored therein. Memory areas and the logic portions of each memory/logic cell can be arranged on the substrate in a shape of an L, U, S, T, or Z to form a pair of interlocking memory/logic cells.