The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 02, 2007
Filed:
Feb. 19, 2004
Applicants:
Vincent Hool, Fremont, CA (US);
John Yuanlin Xie, Fremont, CA (US);
Inventors:
Vincent Hool, Fremont, CA (US);
John Yuanlin Xie, Fremont, CA (US);
Assignee:
Altera Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 23/48 (2006.01); H05K 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract
Methods and apparatus are provided for designing the electrical interconnects of a substrate. Modules are used to design sections of the electrical interconnects. Multiple modules may be interconnected to generate the electrical interconnects. The placement of modules and/or the interconnection of the modules may depend on a netlist and/or a separate report. Modules may even be defined by various constraints. Accordingly, a module based design may be implemented for efficiently and effectively producing a standardized electrical interconnect design.