The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 25, 2007
Filed:
Mar. 21, 2002
Applicants:
Sunil Talwar, Warwickshire, GB;
Dmitrity Rumynin, Coventry, GB;
Inventors:
Sunil Talwar, Warwickshire, GB;
Dmitrity Rumynin, Coventry, GB;
Assignee:
Arithmatica Limited, Oxford, GB;
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/52 (2006.01);
U.S. Cl.
CPC ...
Abstract
A multiplication logic circuit comprises array generation logic and array reduction logic. The array reduction logic comprises array reduction logic for a first level of array reduction which comprises maximal length parallel counters for reducing maximal length columns. The output of the maximal length parallel counters are then further reduced by a second level of reduction logic comprising logic circuits with asymmetric delays in order to compensate for the differential delays experienced by the outputs of the maximal length parallel counters.