The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 25, 2007
Filed:
Jan. 03, 2006
Hiroshi Furuta, Kanagawa, JP;
Kenjyu Shimogawa, Kanagawa, JP;
Ichirou Mizuguchi, Kanagawa, JP;
Junji Monden, Kanagawa, JP;
Shinji Takeda, Kanagawa, JP;
Hiroshi Furuta, Kanagawa, JP;
Kenjyu Shimogawa, Kanagawa, JP;
Ichirou Mizuguchi, Kanagawa, JP;
Junji Monden, Kanagawa, JP;
Shinji Takeda, Kanagawa, JP;
NEC Electronics Corporation, Kawasaki, Kanagawa, JP;
Abstract
An integrated circuit apparatus includes a SRAM cell array having a plurality of memory cells formed of CMOSFET arranged lattice-like. The SRAM cell array has a pair of power line and ground line in each of 1-bit sequences. The integrated circuit apparatus also includes a detector detecting the occurrence of latch-up for each 1-bit sequence and outputting a detection signal, and a power controller controlling a power supply voltage to the power line for each 1-bit sequence. The power controller reduces a voltage to be supplied to the power line in the 1-bit sequence where latch-up is occurring down to a predetermined value according to the detection signal.