The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 11, 2007

Filed:

Aug. 08, 2003
Applicants:

Mutsumi Kikuchi, Hitachi, JP;

Noboru Akiyama, Hitachinaka, JP;

Hiroyuki Shoji, Hitachi, JP;

Fumio Murabayashi, Naka, JP;

Akihiko Kanouda, Hitachinaka, JP;

Takashi Sase, Hitachi, JP;

Koji Tateno, Hitachi, JP;

Inventors:

Mutsumi Kikuchi, Hitachi, JP;

Noboru Akiyama, Hitachinaka, JP;

Hiroyuki Shoji, Hitachi, JP;

Fumio Murabayashi, Naka, JP;

Akihiko Kanouda, Hitachinaka, JP;

Takashi Sase, Hitachi, JP;

Koji Tateno, Hitachi, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device capable of achieving downsizing without reducing the power supply efficiency and capable of reducing switching noises and a memory card using the same are disclosed. The device comprises a plurality of stages of voltage booster circuits for potentially raising a power supply voltage up to a final output voltage, a voltage control unit for controlling an output voltage at a nearby location of the final stage, and one or more internal elements to which the final output voltage is supplied. A primary voltage booster circuit at the first stage includes an inductance element, a switching element, a diode and a driver circuit. At a metal core part of the inductance element, a metal wiring line is used, which was formed by use of a fabrication process of semiconductor integrated circuits, while employing for its core part an inter-wiring layer dielectric film that was formed using the fabrication process. In addition, the switching element and the diode are arranged so that portions thereof are disposed beneath the inductance element.


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