The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 04, 2007
Filed:
May. 07, 2004
Ahmed Rashid Syed, Santa Clara, CA (US);
Ahmed Rashid Syed, Santa Clara, CA (US);
Credence Systems Solutions, Milpitas, CA (US);
Abstract
The present invention relates to test systems for testing integrated circuit devices and to calibration associated systems and methods. One embodiment of the invention provides a test system formatter including: a plurality of event logic interfaces, each event logic interface capable of receiving and decoding timing signals; a plurality of delay line elements (DLEs), each DLE being coupled to a corresponding event logic interface and being capable of generating timing markers corresponding to signals received from the corresponding event logic interface; drive logic coupled to the plurality of DLEs, having first and second outputs and operative to produce first and second formatted levels on the first and second outputs in response to timing markers received from the plurality of DLEs; response logic coupled to the plurality of DLEs, having first and second inputs and operative to produce strobe markers in response to timing markers received from the plurality of DLEs; and a loop-back circuit.