The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 04, 2007

Filed:

Jan. 13, 2005
Applicants:

Edward R. Pillai, Wappingers Falls, NY (US);

Louis L. Hsu, Fishkill, NY (US);

Wolfgang Sauter, Richmond, VT (US);

Daniel W. Storaska, Walden, NY (US);

Inventors:

Edward R. Pillai, Wappingers Falls, NY (US);

Louis L. Hsu, Fishkill, NY (US);

Wolfgang Sauter, Richmond, VT (US);

Daniel W. Storaska, Walden, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H02H 3/22 (2006.01);
U.S. Cl.
CPC ...
Abstract

A chip is provided in which an on-chip matching network has a first terminal conductively connected to a bond pad of the chip and a second terminal conductively connected to a common node on the chip. A wiring trace connects the on-chip matching network to a circuit of the chip. The on-chip matching network includes an electrostatic discharge protection (ESD) circuit having at least one diode having a first terminal conductively connected to the bond pad and a second terminal connected in an overvoltage discharge path to a source of fixed potential. The matching network further includes a first inductor coupled to provide a first inductive path between the bond pad and the wiring trace, a termination resistor having a first terminal connected to the common node, and a second inductor coupled to provide a second inductive path between the wiring trace and a second terminal of the termination resistor.


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