The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 04, 2007
Filed:
Jul. 01, 2005
Tsu-jae King, Fremont, CA (US);
Victor Moroz, Saratoga, CA (US);
Tsu-Jae King, Fremont, CA (US);
Victor Moroz, Saratoga, CA (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a 'corrugated substrate'), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and 'wrapped' gates can be used in conjunction with the segmented channel regions to further enhance device performance.