The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 04, 2007
Filed:
Nov. 14, 2005
Voon-yew Thean, Austin, TX (US);
Brian J. Goolsby, Austin, TX (US);
Linda B. Mccormick, Dripping Springs, TX (US);
Bich-yen Nguyen, Austin, TX (US);
Colita M. Parker, Austin, TX (US);
Mariam G. Sadaka, Austin, TX (US);
Victor H. Vartanian, Dripping Springs, TX (US);
Ted R. White, Austin, TX (US);
Melissa O. Zavala, Pflugerville, TX (US);
Voon-Yew Thean, Austin, TX (US);
Brian J. Goolsby, Austin, TX (US);
Linda B. McCormick, Dripping Springs, TX (US);
Bich-Yen Nguyen, Austin, TX (US);
Colita M. Parker, Austin, TX (US);
Mariam G. Sadaka, Austin, TX (US);
Victor H. Vartanian, Dripping Springs, TX (US);
Ted R. White, Austin, TX (US);
Melissa O. Zavala, Pflugerville, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.