The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 28, 2007

Filed:

Nov. 24, 2004
Applicants:

Jian-yuan Shen, Hsinchu, TW;

Hsien-wen Hsu, Hsinchu, TW;

Chi-ling Chu, Hsinchu, TW;

Inventors:

Jian-Yuan Shen, Hsinchu, TW;

Hsien-Wen Hsu, Hsinchu, TW;

Chi-Ling Chu, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/06 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

An ultra cycling nitride read only memory (NROM) device is coupled to a NROM array such that both bits of the ultra cycling NROM device will be erased when all NROM devices of the NROM array are erased. The ultra cycling NROM device is then programmed at its right bit. A threshold voltage difference will be obtained for the ultra cycling NROM device for the un-programmed left bit. Next, a cycling number is obtained based on the threshold voltage difference for the ultra cycling NROM device. A threshold voltage shift can be found based on the cycling number for the NROM array. Finally, an erase voltage will be calculated according to the threshold voltage shift for the NROM array. If the NROM array is programmed again, the erase voltage will be applied to un-programmed NROM devices of the NROM array to further reduce the threshold voltages.


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