The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 28, 2007
Filed:
Dec. 13, 2004
Ching-hsiang Hsu, Hsin-Chu, TW;
Shih-jye Shen, Hsin-Chu, TW;
Hsin-ming Chen, Tainan Hsien, TW;
Hai-ming Lee, Taipei, TW;
Ching-Hsiang Hsu, Hsin-Chu, TW;
Shih-Jye Shen, Hsin-Chu, TW;
Hsin-Ming Chen, Tainan Hsien, TW;
Hai-Ming Lee, Taipei, TW;
eMemory Technology Inc., Hsin-Chu, TW;
Abstract
A memory cell includes an N-type well, three P-type doped regions, a first stacked dielectric layer, a first gate, a second stacked dielectric layer, and a second gate. The three P-type doped regions are formed on the N-well. The first dielectric stack layer is formed on the N-type well and between the first doped region and the second doped region from among the three P-type doped regions. The first gate is formed on the first stacked dielectric layer. The second stacked dielectric layer is formed on the N-type well and between the second doped region and the third doped region from among the three P-type doped regions. The second gate is formed on the second stacked dielectric layer.