The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 28, 2007
Filed:
Aug. 03, 2005
John Lin, Chelmsford, MA (US);
Tony T. Phan, Flower Mound, TX (US);
Philip L. Hower, Concord, MA (US);
William C. Loftin, Plano, TX (US);
Martin B. Mollat, McKinney, TX (US);
John Lin, Chelmsford, MA (US);
Tony T. Phan, Flower Mound, TX (US);
Philip L. Hower, Concord, MA (US);
William C. Loftin, Plano, TX (US);
Martin B. Mollat, McKinney, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
The present invention provides an integrated circuit and a method of manufacture therefor. The integrated circuit (), in one embodiment without limitation, includes a dielectric layer () located over a wafer substrate (), and a semiconductor substrate () located over the dielectric layer (), the semiconductor substrate () having one or more transistor devices () located therein or thereon. The integrated circuit () may further include an interconnect () extending entirely through the semiconductor substrate () and the dielectric layer (), thereby electrically contacting the wafer substrate (), and one or more isolation structures () extending entirely through the semiconductor substrate () to the dielectric layer ().