The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 21, 2007
Filed:
Mar. 16, 2005
Doo-hoon Goo, Hwaseong-si, KR;
Si-hyeung Lee, Hwaseong-si, KR;
Han-ku Cho, Seongnam-si, KR;
Sang-gyun Woo, Yongin-si, KR;
Gi-sung Yeo, Seoul, KR;
Doo-hoon Goo, Hwaseong-si, KR;
Si-hyeung Lee, Hwaseong-si, KR;
Han-ku Cho, Seongnam-si, KR;
Sang-gyun Woo, Yongin-si, KR;
Gi-sung Yeo, Seoul, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
There are provided a method of forming a trench for a recessed channel of a transistor and a layout for the same. A layout for the recessed channel according to one aspect of the present invention is formed such that an open region is extended across at least one of a first active region in a lateral direction, and also across another second active region in parallel with the first active region in a diagonal direction, and the extension is cut not to reach an isolation region between two third active regions that are in parallel with the second active region in a diagonal direction, and have noses facing each other in a longitudinal direction, and the layout includes an alignment of a plurality of open regions, which are discontinuously aligned. An etch mask is formed using the layout, and a semiconductor substrate is etched using the etch mask, and a trench for a recessed channel is formed on the active region.