The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2007

Filed:

Nov. 15, 2002
Applicants:

Hideki Osaka, Kawasaki, JP;

Toyohiko Komatsu, Kawasaki, JP;

Masashi Horiguchi, Kodaira, JP;

Susumu Hatano, Kodaira, JP;

Kazuya Ito, Kodaira, JP;

Inventors:

Hideki Osaka, Kawasaki, JP;

Toyohiko Komatsu, Kawasaki, JP;

Masashi Horiguchi, Kodaira, JP;

Susumu Hatano, Kodaira, JP;

Kazuya Ito, Kodaira, JP;

Assignee:

Elpida Memory, Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A clock is located at a position close to a plurality of memory modules connected to a memory controller and located away from the controller, and wiring is carried out so that read access is preferential for transmission of read data. With respect to write data, a delay amount corresponding to a round-trip propagation delay time to each of the modules is measured and writing of the write data is carried out while maintaining a known time relationship between the clock and data. To measure round-trip reflection, lines are wired between the modules and a location detection circuit in a 1:1 relationship, and the circuit measures a time taken from a signal output time of a driver having the same impedance as that of the wired lines to a reflected-wave reception time of a hysteresis receiver.


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