The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 07, 2007

Filed:

Jul. 13, 2004
Applicants:

Herng-jer Lee, Tao-Yuan, TW;

Chia-chi Chu, Tao-Yuan, TW;

Wu-shiung Feng, Tao-Yuan, TW;

Ming-hong Lai, Tao-Yuan, TW;

Inventors:

Herng-Jer Lee, Tao-Yuan, TW;

Chia-Chi Chu, Tao-Yuan, TW;

Wu-Shiung Feng, Tao-Yuan, TW;

Ming-Hong Lai, Tao-Yuan, TW;

Assignee:

Chang Gung University, Tao-Yuan, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 17/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

A moment computation technique for general lumped R(L)C interconnect circuits with multiple resistor loops is proposed. Using the concept of tearing, a lumped R(L)C network can be partitioned into a spanning tree and several resistor links. The contributions of network moments from each free and the corresponding links can be determined independently. By combining the conventional moment computation algorithms and the reduced ordered binary decision diagram (ROBDD), the proposed method can compute system moments efficiently. Experimental results demonstrate that the proposed method can indeed obtain accurate moments and is more efficient than the conventional approach.


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