The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 07, 2007

Filed:

Jul. 28, 2004
Applicants:

Subahu D. Desai, Vestal, NY (US);

How T. Lin, Vestal, NY (US);

John M. Lauffer, Waverly, NY (US);

Voya R. Markovich, Endwell, NY (US);

David L. Thomas, Endicott, NY (US);

Inventors:

Subahu D. Desai, Vestal, NY (US);

How T. Lin, Vestal, NY (US);

John M. Lauffer, Waverly, NY (US);

Voya R. Markovich, Endwell, NY (US);

David L. Thomas, Endicott, NY (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/58 (2006.01);
U.S. Cl.
CPC ...
Abstract

A circuitized substrate comprised of at least one dielectric material having an electrically conductive pattern thereon. At least part of the pattern is used as the first layer of an organic memory device which further includes at least a second dielectric layer over the pattern and a second pattern aligned with respect to the lower part for achieving several points of contact to thus form the device. The substrate is preferably combined with other dielectric-circuit layered assemblies to form a multilayered substrate on which can be positioned discrete electronic components (e.g., a logic chip) coupled to the internal memory device to work in combination therewith. An electrical assembly capable of using the substrate is also provided, as is an information handling system adapted for using one or more such electrical assemblies as part thereof.


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