The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 31, 2007
Filed:
Dec. 23, 2004
Kaname Ozawa, Kawasaki, JP;
Mitsutaka Sato, Kawasaki, JP;
Tetsuya Fujisawa, Kawasaki, JP;
Yoshiyuki Yoneda, Kawasaki, JP;
Ryuji Nomoto, Kawasaki, JP;
Yoshitaka Aiba, Kawasaki, JP;
Kaname Ozawa, Kawasaki, JP;
Mitsutaka Sato, Kawasaki, JP;
Tetsuya Fujisawa, Kawasaki, JP;
Yoshiyuki Yoneda, Kawasaki, JP;
Ryuji Nomoto, Kawasaki, JP;
Yoshitaka Aiba, Kawasaki, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A method of design of a circuit board enabling high density conductor lines to be drawn efficiently. A rats nest is formed by connecting pads to which terminals of an electronic device are connected and external connection terminals by lines. A region with the highest density of lines of the rats nest is then selected and design rules relating to routes and dimensions of conductor lines are set in the region with the highest density of lines of the rats nest. Conductor lines are then laid at the region with the highest density of lines of the rats nest, and whether or not the conductor lines can be laid at the region with the highest density of lines of the rats nest is confirmed. Setting of the design rules and laying of conductor lines are if the conductor lines cannot be laid, and the conductor lines of the remaining regions are laid by the set design rules if the conductor lines can be laid.