The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 31, 2007
Filed:
Sep. 27, 2004
Prasenjit Biswas, Lowell, MA (US);
Ramesh S. Mayiladuthurai, Santa Clara, CA (US);
Chandrashekar L. Chetput, Santa Clara, CA (US);
Abhijeet Kolpekwar, New Berlin, WI (US);
Prasenjit Biswas, Lowell, MA (US);
Ramesh S. Mayiladuthurai, Santa Clara, CA (US);
Chandrashekar L. Chetput, Santa Clara, CA (US);
Abhijeet Kolpekwar, New Berlin, WI (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A method for connecting Verilog-AMS and VHDL-AMS components in a mixed-language mixed-signal design includes receiving a mixed-language mixed-signal design, where the mixed-language mixed-signal design comprises one or more VHDL-AMS and Verilog-AMS components, including a first VHDL-AMS component and a first Verilog-AMS component. The method further includes receiving a predetermined set of connection rules, resolving incompatibilities between the first VHDL-AMS component and the first Verilog-AMS component in accordance with the predetermined set of connection rules, and connecting the first VHDL-AMS component to the first Verilog-AMS component.