The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 31, 2007

Filed:

Jan. 12, 2004
Applicants:

Roger D. Isaac, Austin, TX (US);

Mitchell Alsup, Austin, TX (US);

Rama S. Gopal, Austin, TX (US);

James K. Pickett, Austin, TX (US);

Michael A. Filippo, Manchaca, TX (US);

Inventors:

Roger D. Isaac, Austin, TX (US);

Mitchell Alsup, Austin, TX (US);

Rama S. Gopal, Austin, TX (US);

James K. Pickett, Austin, TX (US);

Michael A. Filippo, Manchaca, TX (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A cache memory subsystem including a fixed latency read/write pipeline. The cache memory subsystem includes a cache storage which may be configured to store a plurality of cache lines of data. The cache memory subsystem further includes a scheduler which may be configured to schedule reads and writes of information associated with the cache storage using a fixed latency pipeline. In response to scheduling a read request, the scheduler may be further configured to cause an associated write to occur a fixed number of cycles after the scheduling of the read request.


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