The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 24, 2007
Filed:
Feb. 03, 2004
Frank J. Juskey, Apopka, FL (US);
Daniel K. Lau, San Francisco, CA (US);
Frank J. Juskey, Apopka, FL (US);
Daniel K. Lau, San Francisco, CA (US);
Advanced Interconnect Technologies Limited, Fort Louis, MU;
Abstract
A method and apparatus for forming a multiple semiconductor die assembly () having a thin profile are presented. The semiconductor die assembly () comprises a plurality of die packages (), with each die package () including a lead frame () having a plurality of leads () each having a down set portion () extending from (). A semiconductor die () is disposed in a central region () of the lead frame () and is electrically connected (). An encapsulant () is disposed in the central region () and covers to the semiconductor die () and a portion (). The first surface () of the leads () and a first surface () of the semiconductor die () are substanial exposed from the encapsulant (). The first surface () of the semiconductor die () and the down set portions () form a cavity (). The semiconductor die packages () are stacked such that at least a portion of the encapsulant () is disposed in the cavity of a next higher semiconductor die package () in the stack.