The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 24, 2007
Filed:
Feb. 13, 2003
Jong Wook Lee, Tokyo, JP;
Hisashi Takemura, Tokyo, JP;
Jong Wook Lee, Tokyo, JP;
Hisashi Takemura, Tokyo, JP;
NEC Corporation, , JP;
Abstract
In a FET having a thin-film SOI layer, to prevent a parasitic resistance increase in source/drain regions. To realize an elevated layer to be formed on the source/drain region without using a lithography process and without a fear of a short circuit. Element-isolation insulating films, which are taller than a semiconductor layer, are formed surrounding the island-shaped semiconductor layer (SOI layer), while gate electrodeswhich are taller than the element-isolation insulating filmsare formed on the semiconductor layer. A polycrystalline silicon filmis deposited on the whole surface. elevated layerswhich are shorter than the element-isolation insulating filmare formed on the source/drain regionsby chemical-mechanical polishing and etching back. Silicide layerstoare formed on the gate electrode and on the elevated layers. An interlayer insulating filmis formed, and a metal electrodeis formed.