The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 24, 2007
Filed:
Nov. 10, 2005
Fu-hsin Chen, Jhudong Township, Hsinchu County, TW;
Wen-hua Huang, Hsinchu, TW;
Kuo-ting Lee, Yongho, TW;
You-kuo Wu, Sizhih, TW;
An-min Chiang, Hsinchu, TW;
Fu-Hsin Chen, Jhudong Township, Hsinchu County, TW;
Wen-Hua Huang, Hsinchu, TW;
Kuo-Ting Lee, Yongho, TW;
You-Kuo Wu, Sizhih, TW;
An-Min Chiang, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
A method is disclosed for integrally forming at least one low voltage device and at least one high voltage device. According to the method, a first gate structure and a second gate structure are formed on a semiconductor substrate, wherein the first and second gate structures are isolated from one another. One or more first double diffused regions are formed adjacent to the first gate structure in the semiconductor substrate. One or more second double diffused regions are formed adjacent to the second gate structure in the semiconductor substrate. One or more first source/drain regions are formed within the first double diffused regions. One or more second source/drain regions are formed within the second double diffused regions. The first double diffused regions function as one or more lightly doped source/drain regions for the low voltage device.