The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 24, 2007
Filed:
Jan. 05, 2005
Cliff Hou, Taipei, TW;
Li-chun Tien, Tainan, TW;
Ching-hao Shaw, Plano, TX (US);
Wan-pin Yu, San Jose, CA (US);
Chia-lin Cheng, Tao-Yuan, TW;
Lee-chung LU, Taipei, TW;
Cliff Hou, Taipei, TW;
Li-Chun Tien, Tainan, TW;
Ching-Hao Shaw, Plano, TX (US);
Wan-Pin Yu, San Jose, CA (US);
Chia-Lin Cheng, Tao-Yuan, TW;
Lee-Chung Lu, Taipei, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
Methods of supplying voltages to integrated circuits are provided. A high voltage VddH and/or a low voltage VddL can be supplied to a filler cell and routed to other cells. Each of the VddH and VddL is carried by one of a first voltage supply wire and a second voltage supply wire. A voltage routing wire routes desired voltage(s) to a filler cell. The first and the second voltage supply wires are preferably formed parallel to the voltage routing wire with their edges substantially aligned to the edges of the voltage routing wire. Vias are made to route the desire voltage. Also preferably, the first voltage supply wire is an Mwire formed outside the filler cell while the second voltage supply wire is an Mwire formed inside the filler cell.