The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7245682 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 17, 2007

Filed:

Sep. 30, 2002
Applicants:

Jen-tai Hsu, El Dorado Hills, CA (US);

Hing-yan to, Cupertino, CA (US);

Andrew M. Volk, Granite Bay, CA (US);

Inventors:

Jen-Tai Hsu, El Dorado Hills, CA (US);

Hing-Yan To, Cupertino, CA (US);

Andrew M. Volk, Granite Bay, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

In some embodiments, a phase detector receives a set of sampling clock signals and a data signal and compares each of the clock signals to the data signal. A clock selector selects an optimal sampling clock signal from the set of sampling clock signals based on a trend of a relationship between the clock signals and the data signal. Other embodiments are described and claimed.


Find Patent Forward Citations

Hsu, Jen-Tai. (2007). Determining an optimal sampling clock (U.S. Patent No. 7245682). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7245682

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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