The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 17, 2007
Filed:
Jul. 21, 2005
Huilong Zhu, Poughkeepsie, NY (US);
Brian L. Tessier, Poughkeepsie, NY (US);
Huicai Zhong, Wappingers Falls, NY (US);
Ying LI, Newburgh, NY (US);
Huilong Zhu, Poughkeepsie, NY (US);
Brian L. Tessier, Poughkeepsie, NY (US);
Huicai Zhong, Wappingers Falls, NY (US);
Ying Li, Newburgh, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
Methods are disclosed for forming dual stressed layers in such a way that both undercutting and an undesirable residual spacer of the first-deposited stressed layer are prevented. In one embodiment, a method includes forming a first stressed silicon nitride layer over the NFET and the PFET, forming a sacrificial layer over the first stressed silicon nitride layer such that the sacrificial layer is thinner over substantially vertical surfaces than over substantially horizontal surfaces, forming a mask over a first one of the NFET and the PFET, removing the first stressed silicon nitride layer over a second one of the NFET and the PFET, and forming a second stressed silicon nitride layer over the second one of the NFET and the PFET. The sacrificial layer prevents undercutting and forming of an undesirable residual spacer during removal of the first-deposited stressed layer.