The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 10, 2007

Filed:

Jan. 14, 2005
Applicants:

Sunil D. Mehta, San Jose, CA (US);

Kerry Ilgenstein, Austin, TX (US);

Inventors:

Sunil D. Mehta, San Jose, CA (US);

Kerry Ilgenstein, Austin, TX (US);

Assignee:

Lattice Semiconductor Corporation, Hillsboro, OR (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
Abstract

In one embodiment, an EEPROM device having voltage limiting charge pumping circuitry includes charge-pumping circuitry that limits the voltage supplied to the high voltage transistors to levels below the breakdown field of the tunnel oxide layer. The EEPROM device includes a substrate having a programming region, a tunnel region, a sensing region, and a low voltage region. A first oxide layer having a first thickness overlies the tunnel region and the sensing region. A second oxide layer having a second thickness overlies the low voltage region. The first oxide thickness is greater than the second oxide thickness. A charge pumping circuit is coupled to the programming region and to the tunnel region. The charge pumping circuit impresses a voltage level across the first oxide layer that is below the field breakdown voltage of first oxide layer.


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