The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 10, 2007
Filed:
Oct. 20, 2004
Applicants:
William George En, Milpitas, CA (US);
Eric N. Paton, Morgan Hills, CA (US);
Scott D. Luning, Poughkeepsie, NY (US);
Inventors:
William George En, Milpitas, CA (US);
Eric N. Paton, Morgan Hills, CA (US);
Scott D. Luning, Poughkeepsie, NY (US);
Assignee:
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/302 (2006.01); H01L 21/461 (2006.01);
U.S. Cl.
CPC ...
Abstract
A gate structure is formed overlying a substrate. A source/drain region of the substrate is exposed to a soluction comprising ammonium hydroxide, hydrogen peroxide, and deionized water to etch an upper-most semiconductor porton of the source/drain region.
En, William. (2007). Methods for post offset spacer clean for improved selective epitaxy silicon growth (U.S. Patent No. 7241700). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7241700
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile