The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 10, 2007
Filed:
Mar. 10, 2004
Sergey Savastiouk, San Jose, CA (US);
Sam Kao, San Mateo, CA (US);
Sergey Savastiouk, San Jose, CA (US);
Sam Kao, San Mateo, CA (US);
Tru-Si Technologies, Inc., Sunnyvale, CA (US);
Abstract
Vias (B) are formed in a surface of a substrate. At least portions of contact pads () are located in the vias. Contact pads () of an integrated circuit structure are inserted into the vias and attached to the contact pads () of the substrate. The vias provide a strong, reliable mechanical and electrical connection. A via may expose not only a contact pad () in the substrate but also a surrounding region. Solder () wets the contact pad better than the surrounding region, resulting in a stronger solder joint and better electrical conductivity. Alternatively, the contact may include multiple conductive layers (), with the top layer () being more solder wettable than the bottom layer () and the top layer covering only a portion of the bottom layer.