The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 03, 2007
Filed:
Aug. 29, 2003
Qiang Wang, Campbell, CA (US);
Sudip K. Nag, San Jose, CA (US);
Srinivasan Dasasathyan, Sunnyvale, CA (US);
James L. Saunders, Mountain View, CA (US);
Pavanish Nirula, San Jose, CA (US);
Qiang Wang, Campbell, CA (US);
Sudip K. Nag, San Jose, CA (US);
Srinivasan Dasasathyan, Sunnyvale, CA (US);
James L. Saunders, Mountain View, CA (US);
Pavanish Nirula, San Jose, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A method () of placing local clock nets in a circuit design can include identifying the local clock nets for the circuit design and selecting components corresponding to each local clock net (), and assigning initial locations to each component of the local clock nets (). The method further can include generating at least one cost function () to evaluate () different placements of components of the local clock nets. The components () of the local clock nets () can be annealed () using one or more of the cost functions to assign locations to each component of the local clock nets.