The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 03, 2007
Filed:
Nov. 22, 2004
Yung-te Lai, Cupertino, CA (US);
Chioumin Chang, San Jose, CA (US);
Kung-chien Chen, Fremont, CA (US);
Chih-chang Lin, San Jose, CA (US);
Yung-Te Lai, Cupertino, CA (US);
Chioumin Chang, San Jose, CA (US);
Kung-Chien Chen, Fremont, CA (US);
Chih-Chang Lin, San Jose, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
An equivalence checking method provides first and second logic functions. Don't care gates are inserted for don't care conditions in the first and second logic functions. The insertion of the don't care gates creates a first intermediate circuit and a second intermediate circuit. All 3DC gates of the first intermediate circuit are propagated and merged into a single 3DC gate when 3DC gates and SDC gates coexist in either of the first and second intermediate circuits. All 3DC gates of the second intermediate circuit are propagated and merged into a single 3DC gate when 3DC gates and SDC gates coexist in either of the first and second intermediate circuits. First and second circuit are produced in response to propagating and merging the 3DC gates. A combinational equivalence check is then performed of the first circuit to the second circuit under different equivalence relations.