Semiconductor memory test apparatus and method for address generation for defect analysis

Abstract

There is disclosed a semiconductor memory test apparatus capable of easily generating an address to be input into a failure analysis memory for testing a memory device having a burst function which automatically generates addresses for banks therein. Each of registers corresponding to the banks of the memory device holds a line address of the corresponding bank. When a start address of one of the banks is input to the memory device, a line address of the same bank as the start address is read out from the register corresponding to the bank and output to a failure analysis memory together with the start address. Furthermore, during burst operation of the bank, the registers output the line address to the failure analysis memory together the same line address as the memory device generated by calculating the start address for each clock cycle.