The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 03, 2007
Filed:
Dec. 13, 2004
Sean Jeffrey Treichler, Mountain View, CA (US);
Brad W. Simeral, San Franciso, CA (US);
David G. Reed, Saratoga, CA (US);
Roman Surgutchik, Santa Clara, CA (US);
Sean Jeffrey Treichler, Mountain View, CA (US);
Brad W. Simeral, San Franciso, CA (US);
David G. Reed, Saratoga, CA (US);
Roman Surgutchik, Santa Clara, CA (US);
NVIDIA Corporation, Santa Clara, CA (US);
Abstract
A system, apparatus, and method are disclosed for increasing the physical memory address space accessible to a processor, at least in part, by translating linear addresses associated with a memory hole into a subset of physical memory addresses that otherwise is inaccessible as system memory by a processor. In one embodiment, a memory controller reclaims memory holes in a system memory divided into ranges of linear addresses, where the system memory includes a number of arbitrarily-sized memory devices. The memory controller includes a memory configuration evaluator configured to determine a translated memory hole size for a memory hole, the memory hole including restricted linear addresses that translate into a subset of physical addresses. Also, memory configuration evaluator can be configured to form adjusted ranges to translate at least one linear address into a subset of physical addresses. As such, the system memory increases by at least the subset of physical addresses.