Formation method of an array source line in nand flash memory

Abstract

Novel fabrication methods permit concurrently forming wordlines, select gates and array source lines in NAND Flash. One method forms oxide and nitride layers of an ONO stack, implants dopants into a source line region to form and unite a source line structure to a source/drain region, forms another oxide and a high-dielectric over the nitride layer, removes the ONOA stack in the source line region, forms a gate oxide in the periphery, and forms an opening in the ONOA stack in an array source line region. The method deposits and selectively removes polysilicon and the high-dielectric concurrently forming wordline and select drain gate structures in bitline contact regions, and select source gate and source line structures in source line regions. The bitline and source line contact regions are implanted to form the source line structure in the source line region and unite the source/drain regions of select source gate structures.