The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 26, 2007
Filed:
Nov. 22, 2004
Laura S. Chadwick, Essex Junction, VT (US);
William R. Corbin, Underhill, VT (US);
Jeffrey H. Dreibelbis, Williston, VT (US);
Erik A. Nelson, Waterbury, VT (US);
Thomas E. Obremski, South Burlington, VT (US);
Toshiharu Saitoh, South Burlington, VT (US);
Donald L. Wheater, Hinesburg, VT (US);
Laura S. Chadwick, Essex Junction, VT (US);
William R. Corbin, Underhill, VT (US);
Jeffrey H. Dreibelbis, Williston, VT (US);
Erik A. Nelson, Waterbury, VT (US);
Thomas E. Obremski, South Burlington, VT (US);
Toshiharu Saitoh, South Burlington, VT (US);
Donald L. Wheater, Hinesburg, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A system for testing a DRAM includes DRAM blocks, the system further includes a processor based built-in self test system for generating a test data pattern, for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block. For each DRAM block, the performing the write of the test pattern into the DRAM block is performed before the performing the pause for the predetermined period of time, and the performing the read of the resulting data pattern from the DRAM block is performed after the performing the pause for the predetermined period of time, and at least a portion of the pause for the predetermined period of time of two or more the DRAM blocks overlap in time.