The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 26, 2007
Filed:
Nov. 18, 2004
Shinichiro Shiratake, Yokohama, JP;
Yukihito Oowaki, Yokohama, JP;
Fumitoshi Hatori, Yokohama, JP;
Mototsugu Hamada, Yokohama, JP;
Hiroyuki Hara, Fujisawa, JP;
Shinichiro Shiratake, Yokohama, JP;
Yukihito Oowaki, Yokohama, JP;
Fumitoshi Hatori, Yokohama, JP;
Mototsugu Hamada, Yokohama, JP;
Hiroyuki Hara, Fujisawa, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A first logic circuit has its supply voltage controlled. A second logic circuit operates in response to an external clock signal. An adjustment circuit includes a first delay circuit supplied with the external clock signal, and a detection circuit which detects a skew between timing of a first clock signal output from the first logic circuit and a second clock signal output from the second logic circuit section. The adjustment circuit adjusts the delay time of the first delay circuit according to the result of the detection by the detection circuit and applies an output signal of the first delay circuit to the first logic circuit as a third clock signal.