The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 26, 2007
Filed:
Apr. 01, 2003
Peter John Mcelheny, Morgan Hill, CA (US);
Yow-juang(bill) W. Liu, San Jose, CA (US);
Jayakannan Jayapalan, San Jose, CA (US);
Francois Gregoire, Cupertino, CA (US);
Peter John McElheny, Morgan Hill, CA (US);
Yow-Juang(Bill) W. Liu, San Jose, CA (US);
Jayakannan Jayapalan, San Jose, CA (US);
Francois Gregoire, Cupertino, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
The present invention is a novel method whereby voids or solid opens at the bottom of via can be avoided without drastically altering the resistivity or parasitic capacitances of the whole metal interconnect system. The invention includes in one embodiment a process of forming interconnects and vias in a microelectronic circuit structure. This process includes implanting and/or alloying an impurity element in the local area of the top surface of a metal interconnect at the bottom of a via. Doping may be done before or after formation of the via. After the via is formed, it is filled with a metal such as copper. Another embodiment of the invention is a microelectronic circuit structure manufactured by the aforementioned method.