Vertical power jfet with low on-resistance for high voltage applications

Abstract

A junction field effect transistor (JFET) has a gate region, drain region, and a source region. An epitaxial region having a first conductivity type is disposed over the drain region. The first conductivity type is N-type semiconductor material. The gate region is disposed within a trench which is formed in the epitaxial region. A P+ region is disposed within the epitaxial region and under the gate region. The P+ region has a first doping concentration of a second conductivity type opposite the first conductivity type. A P− region is disposed under the P+ region. The P− region has a second doping concentration of the second conductivity type which is less than the first doping concentration. The P− region may be disposed adjacent to a first portion of the P+ region while another P− region is disposed adjacent to a second portion of the P+ region. The P+ region may be implanted from the gate region deep into the epitaxial region.