The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 26, 2007
Filed:
May. 11, 2004
Mohsen Hossein Mardi, Fremont, CA (US);
Jae Cho, Saratoga, CA (US);
Xin X. Wu, Fremont, CA (US);
Chih-chung Wu, Hsinchu, TW;
Shih-liang Liang, Chung Li, TW;
Sanjiv Stokes, Los Altos, CA (US);
Hassan K. Bazargan, San Jose, CA (US);
Mohsen Hossein Mardi, Fremont, CA (US);
Jae Cho, Saratoga, CA (US);
Xin X. Wu, Fremont, CA (US);
Chih-Chung Wu, Hsinchu, TW;
Shih-Liang Liang, Chung Li, TW;
Sanjiv Stokes, Los Altos, CA (US);
Hassan K. Bazargan, San Jose, CA (US);
XILINX, Inc., San Jose, CA (US);
Abstract
A semiconductor component having test pads and a method and apparatus for testing the same is described. In an example, an un-bumped substrate is obtained having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. In another example, a substrate is fabricated having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. An insulating layer is formed over the plurality of test pads.