The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 19, 2007

Filed:

Jul. 14, 2005
Applicants:

Tawfik Arabi, Tigard, OR (US);

Hung-piao MA, Portland, OR (US);

Gregory M. Iovino, Hillsboro, OR (US);

Shai Rotem, Hofit, IL;

Avner Kornfeld, Zichron Yaakov, IL;

Gregory F. Taylor, Portland, OR (US);

Inventors:

Tawfik Arabi, Tigard, OR (US);

Hung-Piao Ma, Portland, OR (US);

Gregory M. Iovino, Hillsboro, OR (US);

Shai Rotem, Hofit, IL;

Avner Kornfeld, Zichron Yaakov, IL;

Gregory F. Taylor, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/26 (2006.01);
U.S. Cl.
CPC ...
Abstract

Systems for testing a plurality of integrated circuits at a plurality of frequencies and voltages is disclosed. In one embodiment, a plurality of integrated circuits is tested at least once within a predetermined set of combinations of frequencies and voltages. If the integrated circuit fails testing within any combination of a frequency and voltage within the predetermined set, the integrated circuit is retested at a different predetermined set of combinations of frequencies and voltages. If the integrated circuit fails testing within any combination of a frequency and voltage within the different predetermined set, the integrated circuit is discarded.


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