The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 19, 2007
Filed:
Aug. 08, 2006
Antonio L. P. Rotondaro, Dallas, TX (US);
Mark R. Visokay, Richardson, TX (US);
Luigi Colombo, Dallas, TX (US);
Antonio L. P. Rotondaro, Dallas, TX (US);
Mark R. Visokay, Richardson, TX (US);
Luigi Colombo, Dallas, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A dielectric layer () is formed over a semiconductor () that contains a first region () and a second region (). A polysilicon layer is formed over the dielectric layer () and over the first region () and the second region (). The polysilicon layer can comprise 0 to 50 atomic percent of germanium. A metal layer is formed over the polysilicon layer and one of the regions and reacted with the underlying polysilicon layer to form a metal silicide or a metal germano silicide. The polysilicon and metal silicide or germano silicide regions are etched to form transistor gate regions () and () respectively. If desired a cladding layer () can be formed above the metal gate structures.