The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2007

Filed:

Jun. 26, 2003
Applicants:

Jerry D. Hayes, Milton, VT (US);

Amol Anil Joshi, Essex Junction, VT (US);

Natesan Venkateswaran, Wappingers Falls, NY (US);

William John Wright, Colchester, VT (US);

Inventors:

Jerry D. Hayes, Milton, VT (US);

Amol Anil Joshi, Essex Junction, VT (US);

Natesan Venkateswaran, Wappingers Falls, NY (US);

William John Wright, Colchester, VT (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for performing input/output (I/O) floor planning on an integrated circuit design is disclosed. User design data related to I/O circuit associated with each package pin is initially collected. The collected user design data is then sorted according to operating conditions. Next, an I/O behavioral model and a package model are chosen based on the sorted data. A simulation deck is dynamically built with appropriate operating conditions. Finally, a simulation is performed through a circuit simulator using the chosen I/O behavioral model and the operating conditions.


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