Nonvolatile memory cell with multiple floating gates formed after the select gate

Abstract

In a memory cell () having multiple floating gates (), the select gate () is formed before the floating gates. In some embodiments, the memory cell also has control gates () formed after the select gate. Substrate isolation regions () are formed in a semiconductor substrate (). The substrate isolation regions protrude above the substrate. Then select gate lines () are formed. Then a floating gate layer () is deposited. The floating gate layer is etched until the substrate isolation regions are exposed. A dielectric () is formed over the floating gate layer, and a control gate layer () is deposited. The control gate layer protrudes upward over each select gate line. These the control gates and the floating gates are defined independently of photolithographic alignment. In another aspect, a nonvolatile memory cell has at least two conductive floating gates (). A dielectric layer () overlying the floating gate has a continuous feature that overlies the floating gate and also overlays a sidewall of the select gate (). Each control gate () overlies the continuous feature of the dielectric layer and also overlies the floating gate. In another aspect, substrate isolation regions () are formed in a semiconductor substrate. Select gate lines cross over the substrate isolation regions. Each select gate line has a planar top surface, but its bottom surface goes up and down over the substrate isolation regions. Other features are also provided.