The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2007

Filed:

Mar. 08, 2005
Applicants:

Jong Shik Yoon, Plano, TX (US);

Shirin Siddiqui, Plano, TX (US);

Amitava Chatterjee, Plano, TX (US);

Brian E. Goodlin, Dallas, TX (US);

Karen H. R. Kirmse, Richardson, TX (US);

Inventors:

Jong Shik Yoon, Plano, TX (US);

Shirin Siddiqui, Plano, TX (US);

Amitava Chatterjee, Plano, TX (US);

Brian E. Goodlin, Dallas, TX (US);

Karen H. R. Kirmse, Richardson, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes forming a gate structure () over a substrate (), the gate structure () having L-shaped sidewall spacers () on opposing sidewalls thereof and placing source/drain implants (or) into the substrate () proximate the gate structure (). The method for manufacturing the semiconductor device further includes removing at least a portion of a horizontal segment of the L-shaped sidewall spacers ().


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