The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 05, 2007
Filed:
Jun. 02, 2004
Takanori Yamazoe, Hadano, JP;
Takashi Tase, Tokorozawa, JP;
Junji Shigeta, Fuchu, JP;
Nobutaka Nagasaki, Iruma, JP;
Eiji Yamasaki, Kodaira, JP;
Nobuhiro Oodaira, Akishima, JP;
Kozo Katayama, Tokyo, JP;
Takanori Yamazoe, Hadano, JP;
Takashi Tase, Tokorozawa, JP;
Junji Shigeta, Fuchu, JP;
Nobutaka Nagasaki, Iruma, JP;
Eiji Yamasaki, Kodaira, JP;
Nobuhiro Oodaira, Akishima, JP;
Kozo Katayama, Tokyo, JP;
Renesas, Technology Corp., Tokyo, JP;
Abstract
In a semiconductor integrated circuit device equipped with a flash memory and an EEPROM which are nonvolatile memories, the invention provides a technique that makes it possible to restrict an EEPROM capacity to a minimum necessary amount and reduce a chip area. Data of a minimal size required for one application program and rewritten frequently is stored in the EEPROM, and the EEPROM is configured to have a capacity of about that minimal size. Data of the same size that are respectively handled by other applications and rewritten frequently are stored in the flash memory. With respect to an application that is actually used, its data stored in the flash memory is transferred to the EEPROM and used. Data transfer between the flash memory and the EEPROM is performed if necessary. Consequently, the EEPROM capacity can be reduced and chip area reduction can be achieved.