The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 05, 2007
Filed:
Apr. 26, 2005
Kazuki Sakuma, Higashimurayama, JP;
Masayasu Kawamura, Higashiyamato, JP;
Yasushi Takahashi, Urawa, JP;
Masachika Masuda, Tokorozawa, JP;
Tamaki Wada, Higashimurayama, JP;
Michiaki Sugiyama, Tokyo, JP;
Hirotaka Nishizawa, Fuchu, JP;
Toshio Sugano, Kodaira, JP;
Kazuki Sakuma, Higashimurayama, JP;
Masayasu Kawamura, Higashiyamato, JP;
Yasushi Takahashi, Urawa, JP;
Masachika Masuda, Tokorozawa, JP;
Tamaki Wada, Higashimurayama, JP;
Michiaki Sugiyama, Tokyo, JP;
Hirotaka Nishizawa, Fuchu, JP;
Toshio Sugano, Kodaira, JP;
Elpida Memory, Inc., Tokyo, JP;
Abstract
A semiconductor device is formed by laminating two semiconductor chips with the rear surfaces thereof provided face to face. Each semiconductor chip is provided with an outer lead for clock enable to which the clock enable signal and chip select signal are individually input. On the occasion of making access to one semiconductor chip, the other semiconductor chip is set to the low power consumption mode by setting the clock enable signal and chip select signal to the non-active condition.