The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 05, 2007

Filed:

Oct. 09, 2003
Applicants:

Chong Ming Lin, Sunnyvale, CA (US);

Jay Denning, Redwood City, CA (US);

Ho Yuan Yu, Saratoga, CA (US);

Inventors:

Chong Ming Lin, Sunnyvale, CA (US);

Jay Denning, Redwood City, CA (US);

Ho Yuan Yu, Saratoga, CA (US);

Assignee:

QSpeed Semiconductor Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

An etched substrate structure is augmented by conductive material to provide enhanced electrical and/or thermal performance. A semiconductor device substrate comprising active regions defined on a top surface is masked and etched to define a pattern of blind features in a bottom surface of the substrate. A conductive material is then deposited on the surface of the blind features. The replacement of semiconductor material with the conductive material lowers the resistance between the active elements on the top surface and the bottom surface. The blind features may be placed in proximity to parasitic bipolar transistors in order to increase immunity to latchup. During wafer processing, a pattern of grooves aligned opposite to a scribe street pattern may be etched on the wafer back side in order to facilitate the separation of individual devices.


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