The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 05, 2007
Filed:
Apr. 07, 2005
Da Zhang, Austin, TX (US);
Jing Liu, Austin, TX (US);
Bich-yen Nguyen, Austin, TX (US);
Voon-yew Thean, Austin, TX (US);
Ted R. White, Austin, TX (US);
Da Zhang, Austin, TX (US);
Jing Liu, Austin, TX (US);
Bich-Yen Nguyen, Austin, TX (US);
Voon-Yew Thean, Austin, TX (US);
Ted R. White, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A semiconductor fabrication process includes forming a gate electrode () overlying a gate dielectric () overlying a semiconductor substrate (). First spacers () are formed on sidewalls of the gate electrode (). First s/d trenches () are formed in the substrate () using the gate electrode () and first spacers () as a mask. The first s/d trenches () are filled with a first s/d structure (). Second spacers () are formed on the gate electrode () sidewalls adjacent the first spacers (). Second s/d trenches () are formed in the substrate () using the gate electrode () and the second spacers () as a mask. The second s/d trenches () are filled with a second s/d structure (). Filling the first and second s/d trenches () preferably includes growing the s/d structures using an epitaxial process. The s/d structures () may be stress inducing structures such as silicon germanium for PMOS transistors and silicon carbon for NMOS transistors.