Tri-mode clock generator to control memory array access

Abstract

A clock generator is provided that is compatible with both DDRand DDRapplications. The internal YCLK signal is turned on only when an active read or write occurs on the integrated circuit memory, even though the main chip clock is always running. A circuit block within the clock generator detects when a read or write is active and initiates a YCLK signal on the next falling edge of the internal clock. Two separate mechanisms are used for determining when to terminate the YCLK. One mechanism is a timer path and the other is a path determined by DDRand DDRcontrol signals. The timer path is strictly time based and is the same for DDRand DDRparts or modes of operation. The other signal path is different for DDRand DDRoperating modes. A DDRcontrol signal turns off YCLK at the next rising edge of the internal clock, and a DDRcontrol signal turns off YCLK at the next falling edge of the internal clock.